1. Field of the Invention
The present invention relates to signal line drive circuit in a semiconductor integrated circuit, and more particularly to a signal line drive circuit that can reduce the charge and discharge of current in signal lines.
2. Description of the Related Art
The trend in technology in the semiconductor field in recent years has been toward ever-increasing data transfer rates. For example, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), an increase in the data transfer rate between devices has been realized without raising the operating speed inside devices by providing a plurality of internal interfaces for the I/O bus and data bus and by using prefetch. These innovations are referred to as the DDR (Double Data Rate) technology, and memory in which this technology is used is referred to as DDR memory.
DDR includes DDRI, DDRII, and DDRIII, according to the number of bits by which prefetch is implemented. In DDRI, the number of prefetch bits is 2, in DDRII, the number of prefetch bits is 4, and in DDRIII, the number of prefetch bits is 8. The greater the number of prefetch bits, the greater the level of acceleration of the data transfer rate. In this way, an acceleration of the rate of data transfer between devices can be implemented while maintaining a substantially uniform operating speed inside the semiconductor memory device.
FIG. 1 shows the configuration of a semiconductor memory device of the prior art. Referring to FIG. 1, the semiconductor memory device of the prior art includes: input/output pad 141, input/output circuit 142, two data bus signal lines D1 and D2, read/write circuit 143, and memory arrays 144. Input/output pad 141 is for exchanging data with devices outside the chip. Input/output circuit 142 controls the input and output of data of the input/output pad.
Read/write circuit 143 includes: read circuit 145, write circuit 146, and I/O bus signal lines IO1 and IO2. Write circuit 146 is connected to data bus signal lines D1 and D2 and I/O bus signal lines IO1 and IO2. Read circuit 145 is connected to data bus signal lines D1 and D2 and I/O bus signal lines IO1 and IO2.
I/O bus signal lines IO1 and IO2 exchange data with memory arrays 144. Read circuit 145 reads data of I/O bus signal lines IO1 and IO2 to data bus signal lines D1 and D2. Write circuit 146 transfers data of data bus signal lines D1 and D2 to I/O bus signal lines IO1 and IO2.
Although only one read/write circuit 143 is shown in the figure, a plurality of read/write circuits is normally provided for the pair of signal lines composed of data bus signal lines D1 and D2. Any one of the plurality of read/write circuits is then selected in accordance with a given address, and the selected circuit then operates. Further, although only one input/output pad 141 is shown in the figure, a single semiconductor memory device is normally provided with a plurality of input/output pads 141.
FIG. 2 is timing charts showing the operation of the semiconductor memory device of the prior art that is shown in FIG. 1 FIG. 2, (A) is a timing chart for a read operation, and (B) is a timing chart for the write operation.
In the read operation, a read command together with an address (external address) is supplied to the semiconductor memory device. In FIG. 2(A), it is assumed that the read command is provided to read circuit 145 at the rise timing ck1 of an external clock signal.
Read circuit 145 selects two-bit memory cells in memory arrays 144 in accordance with the external address. Data DATA1 and DATA2 are simultaneously supplied as output from the memory cell to I/O bus signal lines IO1 and IO2, respectively.
Read circuit 145 next supplies data DATA1 and DATA2 of I/O bus signal lines IO1 and IO2 to data bus signal lines D1 and D2, respectively.
Input/output circuit 142 supplies data DATA1 of data bus signal line D1 to input/output pad 141 at time ck3 that is synchronized with the external clock signal. Input/output circuit 142 next supplies data DATA2 of data bus signal line D2 to input/output pad 141 at time ck3d that is delayed one-half cycle from the external clock signal.
The determination of which of data DATA1 and DATA2 that is supplied first to input/output pad 141 depends on, for example, the value of the least significant bit of the external address. In other words, if the least significant bit A0 of the address is “Low,” data DATA1 is supplied at timing ck3 and data DATA2 is supplied at timing ck3d; and if the least significant bit A0 is “High,” data DATA2 is supplied at timing ck3 and data DATA1 is supplied at timing ck3d. FIG. 2(A) shows an example in which the least significant bit A0 is “Low.”
In the write operation, a write command is supplied together with an address (external address) and data to the semiconductor memory device. In FIG. 2(B), the write command is applied to write circuit 146 at timing ck1 of the rise of the external clock signal.
Input/output circuit 142 takes in data DATA1 of input/output pad 141 at the next rise timing ck2 of the external clock signal. In addition, input/output circuit 142 takes in data DATA2 of input/output pad 141 at timing ck2d that is further delayed a half-cycle.
Input/output circuit 142 supplies data DATA1 as output to data bus signal line D1 and supplies data DATA2 as output to data bus signal line D2 at timing t1. Write circuit 146 next simultaneously supplies data DATA1 of data bus signal line D1 to I/O bus signal line IO1 and data DATA2 of data bus signal line D2 to I/O bus signal line IO2 and writes these data items to two-bit memory cells at the prescribed addresses.
As in the read operation, the determination of which of data DATA1 and data DATA2 that are to be applied first to input/output pad 141 depends on, for example, the value of the least significant bit of the external address. In other words, when the least significant bit A0 of the address is “Low,” data DATA1 are applied first, and when least significant bit A0 is “High,” data DATA2 are applied first. In the following explanation, the least significant bit A0 of the external address is assumed to be “Low” unless otherwise stated.
As shown in FIGS. 2(A) and (B) above, in a DDRI semiconductor memory device of the prior art, read/write operations of two-bit memory cells in memory arrays 144 are carried out in parallel in one step, while the input/output of two bits of data at input/output pad 141 is carried out serially at different timings. The data transfer rate can thus be accelerated without accelerating the read/write operations of the memory cells.
Although DDRI that employs 2-bit prefetch has been described here, DDRII that employs 4-bit prefetch and DDRIII that employs 8-bit prefetch operate according to the same principles. In DDRII, four internal interfaces are required, and eight internal interfaces are required in DDRIII.
With the increases to higher speeds from DDRI to DDRII and from DDRII to DDRIII, the data bus width of the internal interfaces expands, the charge and discharge of current from the data-bus interconnections increases, and the electrical source noise when data are transferred to the data bus increases. On the other hand, with miniaturization of the semiconductor structure, the proportion of capacitance produced by coupling between adjacent signal lines that accounts for the wiring capacitance of signal lines such as data bus signal lines also increases. Coupling capacitance between adjacent signal lines therefore now accounts for the greater part of wiring capacitance.
Current research now focuses on reducing the current consumption that results from the charge and discharge of the coupling capacitance, and further, reducing the power source noise that is produced by charging and discharging, and in recent years, a variety of methods have been investigated for reducing the consumption of current that results from the charge and discharge of coupling capacitance.
A technique known as “data bus inversion” has been disclosed as a method for reducing the consumption of current caused by the charge and discharge of coupling capacitance (for example, refer to Japanese Patent No. 2647344). In the data bus inversion technique, a single determination output signal is conferred to a data bus that is composed of a plurality of signal lines. Next, for each signal line, data that are currently being supplied as output are compared with data that are to be supplied as output.
If the data of a majority of signal lines change, the logic of the next data of all signal lines is inverted and supplied as output. A determination output signal is activated together with this output. If the number of signal lines in which data change does not constitute a majority, the logic of the next data is supplied as non-inverted output. The determination output signal is then deactivated together with this output.
In this way, the number of signal lines in which levels change will always be less than a majority of the number of all signal lines of the data bus, and the consumed current and power source noise of data transfer are consequently reduced.
As another method for reducing the current consumption that results from charging and discharging of coupling capacitance, the transfer timing of each signal line of the data bus can be serially divided (for example, refer to Japanese Patent Laid-Open Publication No. 2002-025265).
FIG. 3 is a timing chart showing the operations of the semiconductor memory device of the prior art in which the transfer timing of each signal is serially divided. The configuration of the semiconductor memory device is assumed to be similar to the device shown in FIG. 1. In FIG. 3, (A) is a timing chart for a read operation, and (B) is a timing chart for a write operation.
In the read operation, a read command is supplied together with an address (external address) to the semiconductor memory device. In FIG. 3(A), the read command is supplied to read circuit 145 at timing ck1 of the rise of the external clock signal.
Read circuit 145 selects two-bit memory cells in memory arrays 144 in accordance with the external address. Data DATA1 and DATA2 from these memory cells are simultaneously supplied to I/O bus signal lines IO1 and IO2, respectively.
Read circuit 145 next supplies data DATA1 of I/O bus signal line IO1 as output to data bus signal line D1 at timing t1. Read circuit 145 then supplies data DATA2 of I/O bus signal line IO2 to data bus signal line D2 at timing t2.
Input/output circuit 142 next supplies data DATA1 of data bus signal line D1 as output to input/output pad 141 at timing ck3 that is synchronized with the external clock signal. Input/output circuit 142 then supplies data DATA2 of data bus signal line D2 to input/output pad 141 at timing ck3d that is delayed one half-cycle from the external clock.
In this read operation, data DATA1 is supplied first to input/output pad 141 and data DATA2 is supplied after, and the transfer of data DATA1 therefore requires high speed, while the need for high speed in the transfer of data DATA2 is low. When data DATA1 change, data DATA2 do not change, whereby the power source noise at such times is lower than a case of simultaneous change and the transfer of data DATA1 can therefore be accelerated.
In a write operation, a write command is supplied to the semiconductor memory device together with an address (external address) and data. In FIG. 3(B), write command is supplied to write circuit 146 at timing ck1 of the rise of the external clock signal.
Input/output circuit 142 takes in data DATA1 of input/output pad 141 at the rise timing ck2 of the next external clock signal. Input/output circuit 142 further takes in data DATA2 of input/output pad 141 at timing ck2d that is delayed a half-cycle.
Input/output circuit 142 next supplies data DATA1 as output to data bus signal line D1 at timing t1. Input/output circuit 142 next supplies data DATA2 as output to data bus signal line D2. Write circuit 146 next supplies data DATA1 of data bus signal line D1 as output to I/O bus signal line IO1, simultaneously supplies data DATA2 of data bus signal line D2 as output to I/O bus signal line IO2, and writes these data to two-bit memory cells of prescribed addresses.
In these write operations, data DATA1 is applied first to input/output pad 141 followed by data DATA2, and the transfer of data DATA1 therefore does not demand high speed, while the transfer of data DATA2 does demand high speed. When data DATA2 change, data DATA1 do not change, and the power source noise at this time is therefore less than for a case of simultaneous change. The transfer of data DATA2 can therefore be realized at higher speed.
Timing t1 of FIG. 3(B) is a timing that precedes timing t1 of FIG. 2(B), and timing t2 of FIG. 3(B) is the same timing as timing t1 of FIG. 2(B).
FIG. 4 shows a typical example of the configuration of the read circuit that is shown in FIG. 1. Referring to FIG. 4, read circuit 145 includes: signal line drive circuits 171 and 172, control circuits 173 and 174, and timing generation circuit 175.
In addition, internal clock signal ICLK, activation signal ACT, and address signal A0 are applied as input to read circuit 145. Internal clock signal ICLK is a clock that is generated based on the external clock. Activation signal ACT is a signal for activating read circuit 145 in accordance with a read command and an external address. Address signal A0 is an address signal of the least significant digit of an external address.
FIG. 4 shows one read circuit 145, and I/O bus signal line and data bus signal line each show one of the plurality of signal lines that make up each bus.
Timing generation circuit 175 supplies an operation timing signal to each of control circuits 173 and 174.
Control circuit 173 is connected to I/O bus signal line IO1 and controls the output from signal line drive circuit 171 to data bus signal line D1 in accordance with the timing signals from timing generation circuit 175. Control circuit 174 is connected to I/O bus signal line IO2 and controls the output from signal line drive circuit 172 to data bus signal line D2 in accordance with the timing signals from timing generation circuit 175.
Signal line drive circuit 171 is a configuration in which n-channel transistor QN1 and p-channel transistor QP1 are connected in a series. Signal line drive circuit 171 drives the signal of data bus signal line D1 with the two transistors QN1 and QP1 under the control of control circuit 173.
Signal line drive circuit 172 is a configuration in which n-channel transistor QN2 and p-channel transistor QP2 are connected in a series. Signal line drive circuit 172 drives the signal of data bus signal line D2 with the two transistors QN2 and QP2 under the control of control circuit 174.
Coupling capacitance C exists between data bus signal line D1 and data bus signal line D2, and in addition, wiring capacitance c1 and c2 exist in each of data bus signal lines D1 and D2.
With the miniaturization of semiconductors, the coupling capacitance of adjacent signal lines tends to increase in signal lines such as buses, and coupling capacitance has therefore become dominant in the wiring capacitance of signal lines in recent years. In data bus signal lines D1 and D2 in FIG. 4, coupling capacitance C accounts for the largest proportion of the wiring capacitance.
While the value of coupling capacitance C between signal lines is normally on the order of several pico (10−12) Farads, the capacitance of the internal interconnections of read circuit 145 and such parts as the gates and diffusion layers of each transistor is on the order of several femto (10−15) Farads. As a result, the total sum of all the capacitance inside read circuit 145 amounts to no more than the order of several hundred femto Farads. The charge and discharge of current of the coupling capacitance accounts for a major portion of the consumed current that is consumed by passage through read circuit 145.
Reference voltage Vss is supplied via Vss pad 176 to read circuit 145. In the supply of reference voltage Vss, the wiring resistance is r1. In addition, a positive power supply voltage Vdd is supplied via Vdd pad 177 to read circuit 145. In the supply of power supply voltage Vdd, the wiring resistance is r2.
At the instant that signal line drive circuits 171 and 172 drive data bus signal lines D1 and D2, a peak current flows through resistance r1 and r2. As a result, the voltage of Vdd interconnections in read circuit 145 falls below power supply voltage Vdd due to the voltage drop at resistance r2. In addition, the voltage of Vss interconnections in read circuit 145 rises above reference voltage Vss. This fluctuation in the power supply voltage and reference voltage causes power source noise.
When power source noise occurs, the difference in voltage between the effective reference voltage Vss and power supply voltage Vdd inside read circuit 145 decreases, and the operating speed of read circuit 145 is reduced. If this peak current can be reduced, the operation of read circuit 145 can be accelerated.
Comparing the operations in FIG. 3(A) and FIG. 2(A), data bus signal lines D1 and D2 in FIG. 3(A) supply output at different timings and the peak current that is consumed in read circuit 145 is therefore reduced, and this operation is therefore able to proceed at a higher speed than the operation in FIG. 2(A).
FIG. 5 shows details of the configuration of the timing generation circuit that is shown in FIG. 4. Referring to FIG. 5, timing generation circuit 175 includes delay circuits DELAY1 and DELAY2 and timing switch circuit 181.
Delay circuits DELAY1 and DELAY2 each provide internal clock signals ICLK that have each been delayed by respective prescribed delay times to timing switch circuit 181. Timing switch circuit 181 generates timing signals based on address signal A0 of the least significant digit of the external address and clocks that have been delayed at delay circuits DELAY1 and DELAY2 and supplies these timing signals to control circuits 173 and 174.
For example, for read circuit 145 to operate at the timings that are shown in FIG. 3(A), delay circuit DELAY1 is set to a delay time such that timing t1 is obtained from internal clock signal ICLK. Further, delay circuit DELAY2 is set to a delay time such that timing t2 is obtained from internal clock signal ICLK.
When address signal A0 is “Low,” timing switch circuit 181 supplies clocks from delay circuit DELAY1 to control circuit 173 and supplies clocks from delay circuit DELAY2 to control circuit 174. When address signal A0 is “High,” timing switch circuit 181 supplies clocks from delay circuit DELAY2 to control circuit 173 and supplies clocks from delay circuit DELAY1 to control circuit 174.
Further, for read circuit 145 to operate at, for example, the timing that is shown in FIG. 2(A), delay circuits DELAY1 and DELAY2 should both be set to a delay time such that timing t1 is obtained from internal clock signal ICLK. Alternatively, a single delay circuit may be provided.
FIG. 6 shows in detail the configuration of the control circuits that are shown in FIG. 4. Control circuit 173 and control circuit 174 have the same configuration, and an example of control circuit 174 is shown in FIG. 6.
Referring to FIG. 6, control circuit 174 includes: amplifier 191, transfer gates TG1 and TG2, inverters INV1-INV5, NAND circuit NAND1, and NOR circuit NOR1.
Amplifier 191 is activated by activation signal ACT, amplifies the signal of I/O bus signal line IO2, and supplies the amplified signal to transfer gate TG1. Transfer gate TG1 turns ON when internal clock signal ICLK is activated. The circuit that is composed of inverters INV1 and INV2 holds the values of node N1 that is connected to the output of transfer gate TG1. The output of transfer gate TG1 is supplied to transfer gate TG2. Transfer gate TG2 turns ON when the timing signal from timing generation circuit 175 is activated. The circuit that is composed of inverter INV3 and INV4 holds the value of node N2 that is connected to the output of transfer gate TG2.
NAND circuit NAND1 finds the NAND logic of the value of node N2 and the value of activation signal ACT and supplies this logic to the gate of transistor QP2. NOR circuit NOR1 finds the NOR logic of the value of node N2 and the value of the signal in which activation signal ACT is inverted by inverter INV5 and supplies this logic to the gate of transistor QN2.
Regarding the operation of control circuit 174, amplifier 191 is first activated when activation signal ACT is activated. During reading, a microvoltage is supplied as output from memory array to I/O bus signal line IO2, and this voltage is amplified to logic level by amplifier 191. In addition, when activation signal ACT is activated, either transistor QN2 or transistor QP2 turns ON in accordance with the value of node N2, and data bus signal line D2 is thus driven.
When internal clock signal ICLK is activated, transfer gate TG1 turns ON and the output of amplifier 191 is transferred to node N1. Next, transfer gate TG2 turns ON in accordance with the timing signal from timing generation circuit 175, and the value of node N1 is transferred to node N2. The output of transfer gate TG2 passes via NAND circuit NAND1 and NOR circuit NOR1 and is supplied to the gates of transistor QN2 and transistor QP2.
Although the details of read circuit 145 have been explained to this point, write circuit 146 can also be realized by a circuit similar to that shown in FIGS. 4–6.
FIG. 7 shows a circuit that is a simplification of the read circuit that is shown in FIG. 4. Referring to FIG. 7, the simplified circuit is composed of signal line drive circuit 201 and drives both of data bus signal lines D1 and D2. In this case, as with FIG. 4, the data bus signal line indicates a single signal line in a data bus.
Signal line drive circuit 201 includes n-channel transistors QN1 and QN2 and p-channel transistors QP1 and QP2.
Transistor QP1 and transistor QN1 are connected in a series between Vss pad 202 to which reference voltage Vss is applied and Vdd pad 203 to which positive power supply voltage Vdd is applied. Similarly, transistor QP2 and transistor QN2 are connected in a series between Vss pad 202 to which reference voltage Vss is applied and Vdd pad 203 to which positive power supply voltage Vdd is applied.
Data bus signal line D1 is driven by the node of transistor QP1 and transistor QN1. Data bus signal line D2 is driven by the node of transistor QP2 and transistor QN2. Coupling capacitance C of the adjacent signal lines is present between data bus signal line D1 and data bus signal line D2. In FIG. 7, the other wiring capacitance that was shown in FIG. 4 has been omitted.
The current that is consumed by the charge and discharge of the coupling capacitance C during read operations and write operations is next considered using the circuit of FIG. 7.
FIG. 8 is a timing chart showing the relation between data bus signal lines D1 and D2 in the operations that are shown in FIGS. 2(A) and (B). Referring to FIG. 8, the data of data bus signal lines D1 and D2 are simultaneously switched at timing t1. The interval preceding timing t1 is here referred to as N, and the interval following timing t1 is referred to as N+1.
The logic of data of data bus signal line D1 in interval N, the logic of data of data bus signal line D2 of interval N, the logic of data of data bus signal line D1 of interval N+1, and the logic of data of data bus signal line D2 of interval N+1 can be either “High” or “Low.” Accordingly, combinations of this logic can take 16 different forms.
FIG. 9 is a table showing the charge that is consumed by the charge and discharge of coupling capacitance C for each of the sixteen combinations of logic in FIG. 8. In the table of FIG. 9, a combination number (No.) is conferred to each of the combinations. In addition, in the table, “L” indicates “Low” level, i.e., reference voltage Vss; and “H” indicates “High” level i.e., power supply voltage Vdd. “V” is the difference in potential between power supply voltage Vdd and reference voltage Vss, and “C” is the value of the coupling capacitance.
The charge consumption of each of sixteen combinations can be classified into the following five patterns.
(Pattern 1)
Pattern 1 is represented by combination No. 1, in which there is no change in data on either of data bus signal lines D1 and D2 between interval N and interval N+1, whereby no charge or discharge of coupling capacitance C occurs, and the consumed charge is 0.
(Pattern 2)
Pattern 2 is represented by combination No. 6. In combination No. 6, data bus signal line D1 changes from L in interval N to H in interval N+1. Similarly, data bus signal line D2 also changes from L in interval N to H in interval N+1. In this case as well, there is no charge or discharge of coupling capacitance C and the consumed charge is therefore 0.
(Pattern 3)
Pattern 3 is represented by combination No. 10. In combination No. 10, data bus signal line D1 changes from “H” in interval N to “L” in interval N+1. In contrast, data bus signal line D2 changes from “L” in interval N to “H” in interval N+1.
FIG. 10 shows the flow of charge in pattern 3. Referring to FIG. 10, charge flows from Vdd pad 203, through transistor QP2, and to data bus signal line D2. Charge further flows through coupling capacitance C to data bus signal line D1. Still further, charge flows through transistor QN1 to Vss pad 202.
By this operation, the difference in potential between data bus signal line D1 and data bus signal line D2 changes from V to −V. In other words, a change in voltage of 2V occurs in the difference in potential, and the charge that flows between Vdd pad 203 and Vss pad 202, i.e., the charge that is consumed by coupling capacitance C, is 2·CV.
(Pattern 4)
Pattern 4 is represented by combination No. 2. In combination No. 2, there is no change in data between interval N and interval N+1 in data bus signal line D1, but a change occurs from “L” in interval N to “H” in interval N+1 in data bus signal line D2.
At this time, the difference in potential between data bus signal line D1 and data bus signal line D2 changes by way of coupling capacitance C from 0 to V. In other words, a change in voltage of V occurs in the difference in potential, and the charge that flows between Vdd pad 203 and Vss pad 202 is 1·CV.
(Pattern 5)
Pattern 5 is represented by combination No. 9. In combination No. 9, a change from “H” in interval N to “L” in interval N+1 occurs in data bus signal line D1, but no change occurs in the data between interval N and interval N+1 in data bus signal line D2.
FIG. 11 shows the flow of charge in pattern 5. Referring to FIG. 11, data bus signal line D1 is “H” and data bus signal line D2 is “L” in interval N. As a result, the difference in potential across the two ends of coupling capacitance C is V, and in this state, a charge of 1·CV is stored in coupling capacitance C. At timing t1, data bus signal line D1 changes from “H” to “L,” whereupon the charge that is stored in coupling capacitance C passes from data bus signal line D1 through transistor QN1. The charge stored in coupling capacitance C is consequently discharged and becomes 0. In addition, the charge that has passed through transistor QN1 passes through transistor QN2 and flows into data bus signal line D2.
By these operations, charge does not flow to Vdd pad 203 and Vss pad 202, and the consumed charge is therefore 0. Further, no charge flows to the wiring resistance of Vdd and Vss, and power source noise is therefore not generated.
FIG. 9 shows the sixteen combinations classified among patterns 1–5 along with the consumed charge. If it is assumed that data are generated randomly in data bus signal lines D1 and D2, the average charge that is consumed by the charge and discharge of coupling capacitance C in a single operation is ( 8/16)·CV=0.5 CV.
FIG. 12 is a timing chart showing the relations between data bus signal lines D1 and D2 in the operations that are shown in FIGS. 3(A) and (B). Referring to FIG. 12, the data of data bus signal line D1 switch at timing t1, and the data of data bus signal line D2 switch at timing t2. In this case, the interval preceding timing t1 is N and the interval following timing t2 is N+1.
In this case as well, the logic for intervals N and N+1 and data bus signal lines D1 and D2 can be combined in sixteen ways.
FIG. 13 is a table showing the charge that is consumed by the charge and discharge of coupling capacitance C for each of the sixteen combinations of logic in FIG. 12. Comparing the charge consumption in the table of FIG. 13 and the table of FIG. 9, there are differences in values for combination Nos. 6, 7, 10, and 11.
In combination No. 6 in FIG. 13, a change from “L” in interval N to “H” in interval N+1 occurs in both data bus signal lines D1 and D2. However, only data bus signal line D1 changes at timing t1, and a charge of 1·CV is consumed in the charging of coupling capacitance C. Coupling capacitance C is discharged at timing t2 and the consumed charge is therefore 0. As a result, the consumed charge from interval N to interval N+1 is 1·CV. Similarly, the consumed charge in combination No. 11 is 1·CV.
In combination No. 10 in FIG. 13, data bus signal line D1 changes from “H” in interval N to “L” in interval N+1, and data bus signal line D2 changes from “L” in interval N to “H” in interval N+1. In this case, a discharge of coupling capacitance C occurs at timing t1 and the consumed charge is therefore 0. At timing t2, the coupling capacitance C is charged and the consumed charge is therefore 1·CV. As a result, the consumed charge from interval N to interval N+1 is 1·CV. Similarly, the consumed charge of combination No. 7 is also 1·CV.
If it is assumed that data are generated randomly in data bus signal lines D1 and D2 in the operations of FIG. 13, the average charge that is consumed by charge and discharge of coupling capacitance C in a single operation is ( 8/16)·CV=0.5 CV.
To facilitate understanding, the explanation focused on the consumption of charge rather than the consumption of current, but the current consumption can be found by dividing this charge consumption by the period of the cycle at which data are switched.
The above-described prior art has the following disadvantages: In the data bus inversion technique, a semiconductor memory device: finds for each of the plurality of signal lines of a data bus whether or not a change has occurred between the data of interval N and the data of interval N+1 as in, for example, the timing chart of FIG. 8; finds whether the number of signal lines in which a change of data has occurred is greater than or less than a majority; and then supplies the data of interval N+1 as output. There is consequently the problem that the output of data is delayed by the time for this calculation.
Further, the operations that are shown in FIG. 3 can be accelerated compared to the operations that are shown in FIG. 2, but the effect of reducing the current consumption that results from the charge and discharge of coupling capacitance cannot be obtained. As explained in Japanese Patent Laid-Open Publication No. 2002-025265, reducing the current consumption caused by these operations has the effect of enabling a simplification of the amplifiers and output circuits for data that are transferred slowly, and consequently, enabling lower power. However, the current that is consumed by elements such as amplifiers or output circuits is minor when compared to the current that is consumed by coupling capacitance, and the effect of lower power is therefore not particularly great.
Finally, according to FIG. 13, the maximum peak current that flows in combination Nos. 7 and 10 in FIG. 9 is reduced by half, whereby a reduction in power source noise and an acceleration of data transfer can be realized. However, the problem still remains that power source noise occurs to a certain extent at timing t1, thereby causing a delay of data transfer.